About project:

Last time I decided to look deeply into electronic IC’s. In this article I described my short journey to the center of a chip – my investigation started from simple layout project in Magic and ended with simulations in LTSpice. As a result of this journey I prepared logic replacement for a CD4001B chip (Quad 2 Input NOR gates). To prepare my project I didn’t use original schematic for CD4001B. My project uses a solution with four transistors, as shown in Picture 2.

Picture 1. The final chip layout

The general assumptions of the project:

• AMIS C5 Techonology,

• Power Supply: 3.3V ±10%,

• Operating Temperature Ranges: -80°C – +125°C,

• Maximum output load: 10pF/20mA,

• Minimal output frequency: 20MHz,

• Metal layer current density: 1mA/μm (electromigration prevention),

• Latchup prevention – max distances between contacts: to base 50μm, to island 15μm,

• PAD’s size: 100μm x 100μm,

• ESD Protection for outputs (as a pair of diodes or p-n-p transistor),

• I/O ring,

Picture 2. CMOS NOR gate schematic

During the implementation of output buffers, the biggest problem was appropriate selection of α and n-values to achieve both maximum output current and a small layout size, so the final size of used transistors were attuned in the first stage of the project and re-adjusted later. In an optimal case – when the delay introduced by the buffer cascade is minimal – α value is equal e (as shown in Picture 3). Because multiplier value can’t be equal e, so I decided to choose bigger value, so that I could decrease the number of stages in the cascade (α=3). To prevent changing of the signal polarization, I finally choose an even n-value (n=4) – maximum output current was unfortunately too small for n=2 value (as I checked by trial and error).

Picture 3. Selection of the appropriate of α-value

Preliminary simulations:

I carried out preliminary simulations.The values estimated in such a way met the basic project assumptions and fulfilled project objectives. As a result of applying this solution, the biggest inverter was build with the pMOS transistor (dimensions: 243×0.6 [μm]) and nMOS (dimensions: 81×0.6 [μm]).

Table 1. Preliminary simulations results

Chip topography:

After obtaining satisfying results of preliminary simulation I started creating first chip layout in Magic. The whole chip has been implemented in hierarchical structure. Cell named “komplet” includes: a buffer, gate, ESD protection circuit, Vcc, and GND pins. On the higher layer, there is a cell named “uklad” which includes four “komplet” cells. Such a solution simplifies the implementation process and the search for potential project errors. The whole chip was surrounded by the I/O ring.

Final simulations:

After layout extraction, I decided that the results of final the simulations are satisfying, so I changed nothing in the first prototype. Output current was 20.34mA in extreme conditions. To achieve such a high output current I had to implement a very huge buffer, which introduced big signal propagation delays (~20ns).

Table 2. Final simulations results

Picture 4. LTSpice simulation – -80°C

Picture 5. LTSpice simulation – +125°C

Project files:

asic_project_cd4001b.zip

Package includes:

• *.mag for all project components,

• *.ext files (layout extraction output),

• *.spice files,